Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor
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Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

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Published by National Aeronautics and Space Administration, Langley Research Center, National Technical Information Service, distributor] in Hampton, Va, [Springfield, Va.? .
Written in English

Subjects:

  • Automatic theorem proving.,
  • Computer algorithms.

Book details:

Edition Notes

StatementJ Strother Moore.
SeriesNASA contractor report -- 189588., NASA contractor report -- NASA CR-189588.
ContributionsLangley Research Center.
The Physical Object
FormatMicroform
Pagination1 v.
ID Numbers
Open LibraryOL14683724M

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Book Jun THE USE OF A FORMAL SIMULATOR TO VERIFY A SIMPLE REAL TIME CONTROL PROGRAM Robert S. Boyer Milton W. Green J Strother Moore ICSCA-CMP July The ease of implementing this parallel approach has also been compared to similar efforts in other shape transformation algorithms. Verified Hardware Implementing an 8-Bit Parallel IO Byzan. Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor by J Strother Moore. August, 37 pages. Consider a network of four processors that use the Oral Messages (Byzantine Generals) algorithm of Pease, Shostak and Lamport to achieve agreement in the presence of faults. J. Strother Moore, Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor, NASA CR, April , pp. 41, The paper is missing figures. Please see of the Frequently Asked Questions (FAQ) for information on how to obtain a hardcopy of this document.

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